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Essentials of High-Level Synthesis Programming and Accelerator Design

NQR Code:NG-05-EH-02910-2024-V1-NIELIT

  • Old Code: NG-05-EH-02910-2024-V1-NIELIT

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About this Qualification

Job Description

This course covers advanced techniques in High-Level Synthesis (HLS) for designing combination and sequential circuits using C/C++. Students will explore the HLS design flow, ports, and propagation delay computation, as well as develop test benches. Topics include IP-centric design flow for sequential circuits, state machines, functional pipelining, and interface synthesis. Additionally, function acceleration on FPGA will be explored through OpenCL concepts, including kernel execution, loop optimization, and memory dependencies.

Eligibility Criteria

Criteria 1 Criteria 2 Experience Training Qualification
UG 2nd year In relevant field No Experience None
3 year Diploma after 10th In relevant field 1.5 Years None
2 year Diploma after 12th In relevant field No Experience None
Previous NSQF qualification of Level 4.5 1.5 Years None
Previous NSQF qualification of Level 4 1.5 Years None

Progression Pathway

  • Design/Application Engineer/Team Lead /Project Manager

Learning Module In Job Role/Qualifcation

National Occupation Standards (NOS)/Module NOS Code Mandatory/ Optional Estimated size (Hours) Nos Credit Level
Essentials of High-Level Synthesis Programming and Accelerator Design NIE/ELE/N0122 Mandatory 60 2 5