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Essentials of System Verilog and UVM based Verification

NQR Code:NG-05-EH-02906-2024-V1-NIELIT
  • Old Code: NG-05-EH-02906-2024-V1-NIELIT

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About this Qualification

Job Description

The Standalone NOS encompasses Integrated Circuit (IC) and System on Chip (SoC) verification, starting with Verilog HDL for RTL verification, test benches, and test automation, then advancing to System Verilog, C/C++, and scripting languages like Linux shell scripting, Perl, and Python. It covers processor architecture, including ISA fundamentals, RISC-V, DIR-V Microprocessors, and bus architecture. SoC verification topics include DIR-V processor-based SoCs, AXI Bus architecture, and various verification methodologies like ABV, CDV, and UVM. The syllabus concludes with SoC emulation, post-silicon validation, FPGA architectures, embedded C programming, and performance benchmarking.

Eligibility Criteria

Criteria 1 Criteria 2 Experience Training Qualification
UG 2nd year In relevant field No Experience None
3 year Diploma after 10th In relevant field 1.5 Years None
2 year Diploma after 12th In relevant field No Experience None
Previous NSQF qualification of Level 4.5 1.5 Years None
Previous NSQF qualification of Level 4 1.5 Years None

Progression Pathway

  • Design Engineer->Application Engineer->Team Lead -> Project Manager

Learning Module In Job Role/Qualifcation

National Occupation Standards (NOS)/Module NOS Code Mandatory/ Optional Estimated size (Hours) Nos Credit Level
Essentials of System Verilog and UVM based Verification NIE/ELE/N0118 Mandatory 60 2 5