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Junior Chip Designer (A-Level 'Chip Design')

NQR Code:QG-05-EH-02594-2024-V1-NIELIT

  • Old Code: QG-05-EH-02594-2024-V1-NIELIT

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About this Qualification

Job Description

Nature: ❖ This VLSI SoC Design and Verification course equips students with essential industry skills for working on SoC projects. The program covers Verilog HDL coding, FPGA architecture, System Verilog-based verification, and FPGA emulation. Emphasis is on processor architectures, bus protocols, and complex scenario verification. Students learn to design and verify SoCs, crucial for employment readiness. Overall, it prepares participants for diverse roles in SoC design, verification, and emulation projects, enhancing their employability and fostering industry innovation. Purpose: ❖ The purpose of A Level chip design program is to equip participants with the necessary skills and knowledge to excel in the field of System-on-Chip (SoC) design, verification, and FPGA emulation.

Eligibility Criteria

Criteria 1 Criteria 2 Experience Training Qualification
UG In relevant field No Experience None
3 year Diploma after 10th In relevant field 1.5 Years None
2 year Diploma after 12th In relevant field No Experience None
Previous NSQF qualification of Level 4.5 1.5 Years None
Previous NSQF qualification of Level 4 3 years None

Progression Pathway

  • Design/Verification/Application Engineer –> Team Lead –> Project Manager

Learning Module In Job Role/Qualifcation

National Occupation Standards (NOS)/Module NOS Code Mandatory/ Optional Estimated size (Hours) Nos Credit Level
VLSI Fundamentals NIE/ELE/N0101 Mandatory 60 2 4
Verilog RTL coding for Synthesis NIE/ELE/N0102 Mandatory 60 2 4
Static Timing Analysis of VLSI Circuits NIE/ELE/N0103 Mandatory 60 2 4
FPGA Architecture and Programming NIE/ELE/N0104 Mandatory 60 2 4
VLSI Verification fundamentals NIE/ELE/N0105 Mandatory 60 2 5
ASIC Verification using System Verilog and UVM NIE/ELE/N0106 Mandatory 60 2 5
VLSI Circuits Design for testability NIE/ELE/N0107 Mandatory 60 2 5
VLSI Physical Design and Verification NIE/ELE/N0108 Mandatory 60 2 5
Accelerator design using HLS programming NIE/ELE/N0109 Mandatory 60 2 5
SOC Design and Verification NIE/ELE/N0110 Mandatory 60 2 5
Employability Skill DGT/VSQ/N0103 Mandatory 90 3 5
OJT/Project NIE/ELE/N0111 Mandatory 90 3 5