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Chip Design Associate (O-Level ‘Chip Design’)

NQR Code:QG-04-EH-02593-2024-V1-NIELIT

  • Old Code: QG-04-EH-02593-2024-V1-NIELIT

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About this Qualification

Job Description

Nature: ❖ This course introduce the students with essential industry skills in VLSI industry. The program covers Verilog HDL coding, FPGA architecture, and FPGA emulation. Overall, the program prepares participants for diverse roles in Physical design, and emulation projects, enhancing their employability and fostering industry innovation. Purpose: ❖ The purpose of O Level chip design program is to introduce the participants with the necessary skills and knowledge to excel in the field of IC design, and FPGA emulation.

Eligibility Criteria

Criteria 1 Criteria 2 Experience Training Qualification
12th In relevant field No Experience None
2 year Diploma after 10th In relevant field No Experience None
Previous NSQF qualification of Level 3.5 1.5 Years None
Previous NSQF qualification of Level 3 3 years None

Progression Pathway

  • Design/Application Engineer –> Team Lead –> Project Manager

Learning Module In Job Role/Qualifcation

National Occupation Standards (NOS)/Module NOS Code Mandatory/ Optional Estimated size (Hours) Nos Credit Level
VLSI Fundamentals NIE/ELE/N0101 Mandatory 60 2 4
Verilog RTL coding for Synthesis NIE/ELE/N0102 Mandatory 60 2 4
Static Timing Analysis of VLSI Circuits NIE/ELE/N0103 Mandatory 60 2 4
Employability Skill DGT/VSQ/N0102 Mandatory 60 2 4
OJT/Project NIE/ELE/N0112 Mandatory 150 5 4